Peripheral Component Interconnect express (PCIe) is a serial bus standard for connecting a computer to one or more peripheral devices. PCIe utilizes a layered protocol consisting of a transaction layer, a data link layer, and a physical (PHY) layer. The data link layer includes a media access control (MAC) layer.
PHY Interface for the PCI Express Architecture (PIPE) is a standard for an interface between the PHY layer and the MAC layer in PCIe Architecture. The PHY layer and the MAC layer utilize clock signals of predetermined frequencies. The clock signals controls when data flows to and from the PHY layer and the MAC layer. Frequencies of the clock signals are determined based on speeds specified by the PCIe protocol. For example, PCIe first generation protocol (Gen1) specifies a data transfer speed of 2.5 Gbps. Accordingly, Gen1 clock signals have a frequency of 125 MHz. PCIe second generation protocol (Gen2) specifies a data transfer speed of 5 Gbps and therefore, Gen2 clocks signals have a frequency of 250 MHz. Similarly, PCIe third generation protocol (Gen3) specifies a data transfer speed of 8 Gbps and have clock signals of frequency 500 MHz. The clock signals utilized by the PHY layer and the MAC layer may have different frequencies.
The differences in frequencies of the clock signals may result in a loss or corruption of data.